Direct Digital Sythesis

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You can read back the value of any of the registers.

, very few had any idea of how it worked, and so an introductory tutorial was going to be in order.

This library expects you to control the profile pins if you want to start and stop sweeps.

The internal PLL clock multiplier defaults to 20, which produces 500MHz from a 25MHz crystal.

The step rate is 8 bit unsigned, expressing a multiple of 4 core clock cycles.

With a 500MHz core clock, the shortest step is 8ns, a step of 125 gets you 1us steps, and the longest step is 2.048us.Ramp-up and ramp-down (amplitude ramping, available when using frequency or phase modulation) is also not available.Instantiate the AD9959 template with the appropriate parameters.The default core frequency is 20 times the reference frequency. Convert the error to parts-per-billion (positive if your frequency is high, negative if it's low). For example if you program 10MHz, but measure 10000043.2Hz, your calibration factor should be 4320.After reset or changing the PLL multiplier, the core clock will take up to 1 millisecond to stabilise.The frequency delta word for a given frequency is obtained using frequency Delta().This conversion uses a 32x32Frequency(My AD9959:: Channel2, 7140000UL); // shorthand for: Delta(My AD9959:: Channel2, dds.frequency Delta(7140000UL)); // 7.14MHz Amplitude(My AD9959:: Channel2, 1023); // Maximum amplitude value Phase(My AD9959:: Channel2, 16383); // Maximum phase value (same as -1) To make a sweep, you must configure the starting signals as above, then either the destination frequency, amplitude or phase, and sweep mode.AD9959 is a chip from Analog Devices for direct digital sythesis of radio frequency signals.With four channels and a 500MHz core frequency, it can coordinate multi-channel sweeps over frequency, amplitude or phase and supports high-rate modulation.You must provide pin numbers for Chip Enable, Reset, and I/O Update.The reference_freq parameter provides your crystal frequency.


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